1. Field of the Invention
The present invention relates to a method of optimizing VLSI circuit designs using manufacturing data and various algorithms to ensure better yields in IC manufacturing.
2. Background of the Invention
The critical area of a very large scale integration (VLSI) layout is a measure that reflects the sensitivity of the layout to random defects that are introduced during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. One model for yield estimation is based on the concept of critical area, which represents the main computational problem in the analysis of yield loss due to random (spot) defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: “extra material” defects causing shorts between different conducting regions and “missing material” defects causing open circuits.
Therefore, it is an object of the invention to provide a means of automatically identifying and analyzing critical areas of an IC circuit layout during the design phase, and reducing the probability of defects by modifying the design. The automated design modification will improve the yields in manufacturing by reducing the probabilities of failures from contaminants or impurities, without creating new design problems. In other words, the method provides constrained optimization.